The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Some network switches store portions of incoming packets in a centralized packet buffer, for example, while egress interfaces for the packets are identified and other processing operations are performed by a packet processor. Packets are later transferred from the centralized packet buffer towards an identified egress interface. In some configurations, the centralized packet buffer is made up of many memory units that are individually addressable, which allows for simultaneous writes to the packet buffer. For example, multiple ingress interfaces can simultaneously write to separate memory units of the centralized packet buffer.